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5.2 Intel ICH6-M South Bridge(8)

General Purpose I/O Signals 1,2

Name Type Tolerance Power Well Description

GPO[49]

OD O V_CPU_I

`Core This signal is fixed as output only and can

instead be used as CPUPWRGD.

GPO[48]

O 3.3 V Core This signal is fixed as output only and can

instead be used as GNT4#.

GPIO[47:42]

N/A N/A N/A This signal is not implemented.

GPI[41]

I 3.3 V Core This signal is fixed as input only and can be used

instead as LDRQ1#.

GPI[40]

I 5 V Core This signal is fixed as input only and can be used

instead as REQ4#.

GPIO[39:35]

N/A N/A N/A This signal is not implemented.

GPIO[34:33]

I/O 3.3 V Core This signal can be input or output and is

unmultiplexed

GPIO[32]

I/O 3.3 V Core This signal can be input or output.

GPI[31]

I 3.3 V Core This signal is fixed as input only and can instead

be used for SATA[3]GP.

GPI[30]

I 3.3 V Core This signal is fixed as input only and can instead

be used for SATA[2]GP.

GPI[29]

I 3.3 V Core This signal is fixed as input only and can instead

be used for SATA[1]GP.

GPIO[28:27]

I/O 3.3 V Resume This signal can be input or output and is

unmultiplexed.

GPI[26]

I 3.3 V Core This signal is fixed as input only and can instead

be used for SATA[0]GP.

GPIO[25]

I/O 3.3 V Resume This signal can be input or output and is

unmultiplexed. It is a strap for internal Vcc2_5

regulator. See Section 2.22.1.

GPIO[24]

I/O 3.3 V Resume This signal can be input or output and is

unmultiplexed.

GPO[23]

O 3.3 V Core This signal is fixed as output only.

GPIO[22]

N/A N/A N/A This signal is not Implemented

GPO[21]

O 3.3 V Core This signal is fixed as output only and is

unmultiplexed

GPO[20]

O 3.3 V Core This signal is fixed as output only.

GPO[19]

O 3.3 V Core This signal is fixed as output only.

NOTE: GPO[19] may be programmed to blink

(controllable by GPO_BLINK (D31:F0:Offset

GPIOBASE+18h:bit 19)).

General Purpose I/O Signals 1,2 (Continued)

Name Type Tolerance Power Well Description

GPO[18]

O 3.3 V Core This signal is fixed as output only.

NOTE: GPO[18] will blink by default

immediately after reset (controllable by

GPO_BLINK (D31:F0:Offset

GPIOBASE+18h:bit 18)).

GPO[17]

O 3.3 V Core This signal is fixed as output only and can be

used instead as PCI GNT[5]#.

GPO[16]

O 3.3 V Core This signal is fixed as output only and can be

used instead as PCI GNT[6]#.

GPI[15:14]3

I 3.3 V Resume This signal is fixed as input only and can be used

instead as OC[7:6]#

GPI[13]3

I 3.3 V Resume This signal is fixed as input only and is

unmultiplexed.

GPI[12]3

I 3.3 V Core This signal is fixed as input only and is

unmultiplexed.

GPI[11]3

I 3.3 V Resume This signal is fixed as input only and can be used

instead as SMBALERT#.

GPI[10:9]3

I 3.3 V Resume This signal is fixed as input only and can be used

instead as OC[5:4]#.

GPI[8]3

I 3.3 V Resume This signal is fixed as input only and is

unmultiplexed.

GPI[7]3

I 3.3 V Core This signal is fixed as input only and is

unmultiplexed.

GPI[6]3

I 3.3 V Core This signal is fixed as input only.

GPI[5:2]3

I 5 V Core This signal is fixed as input only and can be used

instead as PIRQ[H:E]#.

GPI[1:0]3

I 5 V Core This signal is fixed as input only and can be used

instead as PCI REQ[6:5]#.

NOTES:

1.All inputs are sticky. The status bit remains set as long as the input was asserted for two

clocks.GPIs are sampled on PCI clocks in S0/S1. GPIs are sampled on RTC clocks in S3/S4/S5.

2.Some GPIOs exist in the VccSus3_3 power plane. Care must be taken to make sure GPIO

signals are not driven high into powered-down planes. Some ICH6 GPIOs may be connected to

pins on devices that exist in the core well. If these GPIOs are outputs, there is a danger that a

loss of core power (PWROK low) or a Power Button Override event will result in the Intel

ICH6 driving a pin to a logic 1 to another device that is powered down.

3.GPI[15:0] can be configured to cause a SMI# or SCI. Note that a GPI can be routed to either

an SMI# or an SCI, but not both.

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