MiTAC 8050QMA Manuel de service télécharger pdf (Page 25)

50QMA

N/B Maintenance

– Chip-Erase for PP Mode

Single 3.0-3.6V Read and Write Operations

Superior Reliability

Firmware Hub Hardware Interface Mode Supports Intel High Definition Audio

– 5-signal communication interface supporting byte Read and Write

– 33 MHz clock frequency operation

– WP# and TBL# pins provide hardware write protect for entire chip and/or top Boot Block

– Block Locking Register for all blocks

– Standard SDP Command Set

– Data# Polling and Toggle Bit for End-of-Write detection

– 5 GPI pins for system design flexibility

– 4 ID pins for multi-chip selection

1.2.10 Memory System

1.2.10.1 256MB, 512MB, 1GB (x64) 200-Pin DDR2 SDRAM SODIMMs

•

JEDEC-standard 200-pin, small-outline, dual in-line memory module (SODIMM)

• VDD=+1.8V±0.1V, VDDQ=+1.8V±0.1V

MiTac Secret

Confidential Document

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MiTAC 8050QMA Manuel de service Page 25