MiTAC 8050QMA Manuel de service télécharger pdf (Page 26)

50QMA

N/B Maintenance

• JEDEC standard 1.8V I/O (SSTL_18-compatible)

• Differential data strobe (DQS,DQS#) option

• Four-bit prefetch architecture

• Differential clock input (CK,CK#)

• Command entered on each rising CK edge

• DQS edge-aligned with data for Reads

• DQS center-aligned with data for Writes

• Duplicate output strobe (RDQS) option for x8 configuration

• DLL to align DQ and DQS transitions with CK

• Four internal banks for concurrent operation

• Data mask (DM) for masking write data

• Programmable CAS Latency (CL) : 2,3,4 and 5

• Posted CAS additive latency (AL) : 0,1,2,3 and 4

• Write latency = Read latency – 1

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MiTAC 8050QMA Manuel de service Page 26