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5.1 Intel 915PM North Bridge(1)

Host Interface Signals

Signal Name Type Description

HADS# I/O

AGTL+

Host Address Strobe:

The system bus owner asserts HADS# to indicate the first of two

cycles of a request phase. The GMCH can also assert this signal for

snoop cycles and interrupt messages.

HBNR# I/O

AGTL+

Host Block Next Request:

Used to block the current request bus owner from issuing a new

request. This signal is used to dynamically control the CPU bus

pipeline depth.

HBPRI# O

AGTL+

Host Bus Priority Request:

The GMCH is the only Priority Agent on the system bus. It asserts

this signal to obtain the ownership of the address bus. This signal has

priority over symmetric bus requests and will cause the current

symmetric owner to stop issuing new transactions unless the

HLOCK# signal was asserted.

HBREQ0# I/O

AGTL+

Host Bus Request 0#:

The GMCH pulls the processor bus HBREQ0# signal low during

HCPURST#. The signal is sampled by the processor on the

active-to-inactive transition of HCPURST#.

HBREQ0# should be tri-stated after the hold time requirement has

been satisfied.

HCPURST# O

AGTL+

Host CPU Reset:

The CPURST# pin is an output from the GMCH. The GMCH asserts

HCPURST# while RSTIN# is asserted and for approximately 1 ms

after RSTIN# is deasserted. HCPURST# allows the processor to

begin execution in a known state.

HDBSY# I/O

AGTL+

Host Data Bus Busy:

Used by the data bus owner to hold the data bus for transfers

requiring more than one cycle.

HDEFER# O

AGTL+

Host Defer:

Signals that the GMCH will terminate the transaction currently being

snooped with either a deferred response or with a retry response.

HDINV[3:0]# I/O

AGTL+

Host Dynamic Bus Inversion:

Driven along with the HFD[63:0]# signals. Indicates if the associated

signals are inverted or not. HDINVF[3:0]# are asserted such that the

number of data bits driven electrically low (low voltage) within the

corresponding 16-bit group never exceeds 8.

HDINV# Data Bits

HDINV[3]# HD[63:48]#

HDINV[2]# HD[47:32]#

HDINV[1]# HD[31:16]#

HDINV[0]# HD[15:0]#

Host Interface Signals (Continued)

Signal Name Type Description

HDRDY# I/O

AGTL+

Host Data Ready:

Asserted for each cycle that data is transferred.

HA[31:3]# I/O

AGTL+

Host Address Bus:

HA[31:3]# connects to the CPU address bus. During processor cycles

the HA[31:3]# are inputs. The GMCH drives HA[31:3]# during

snoop cycles on behalf of DMI.

HA[31:3]# are transferred at 2x rate.

Note that the address is inverted on the CPU bus.

HADSTB[1:0]# I/O

AGTL+

Host Address Strobe:

HA[31:3]# connects to the CPU address bus. During CPU cycles, the

source synchronous strobes are used to transfer HA[31:3]# and

HREQ[4:0]# at the 2x transfer rate.

Strobe Address Bits

HADSTB[0]# HA[16:3]#, HREQ[4:0]#

HADSTB[1]# HA[31:17]#

HD[63:0]# I/O

AGTL+

Host Data:

These signals are connected to the CPU data bus. HD[63:0]# are

transferred at 4x rate.

Note that the data signals are inverted on the CPU bus depending on

the HDINV[3:0]# signals.

HDSTBP[3:0]#

HDSTBN[3:0]#

I/O

AGTL+

Host Differential Host Data Strobes:

The differential source synchronous strobes are used to transfer

HD[63:0]# and HDINV[3:0]# at the 4x transfer rate.

Strobe Data Bits

HDSTBP[3]#, HDSTBN[3]# HD[63:48]#, HDINV[3]#

HDSTBP[2]#, HDSTBN[2]# HD[47:32]#, HDINV[2]#

HDSTBP[1]#, HDSTBN[1]# HD[31:16]#, HDINV[1]#

HDSTBP[0]#, HDSTBN[0]# HD[15:00]#, HDINV[0]#

HHIT# I/O

AGTL+

Host Hit:

Indicates that a caching agent holds an unmodified version of the

requested line.

Also, driven in conjunction with HITM# by the target to extend the

snoop window.

HHITM# I/O

AGTL+

Host Hit Modified:

Indicates that a caching agent holds a modified version of the

requested line and that this agent assumes responsibility for providing

the line.

Also, driven in conjunction with HIT# to extend the snoop window.

5. Pin Descriptions of Major Components

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MiTAC 8050QMA Manuel de service Page 79

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